U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith. The Lohrey et al patent discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. The emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give a no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the non-conducting one of the two cross-connected transistors.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith. The Berger et al patent discloses a monolithic semiconductor circuit comprising a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semiconductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1974 to S. K. Wiedmann, and of common assignee herewith. The Wiedmann patent discloses a memory cell arrangement which allows the powering of only two row cells at any one time. This results in lower power dissipation in the cells and also permits the driving circuits to operate at a much lower power level, thereby further reducing the power dissipation per chip.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith. The Berger et al patent discloses a digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, an input adapted to receive a digital logic signal, an output, a current source, means connecting said first transistor emitter to said current source, means connecting said first transistor base to said second transistor emitter, means connecting said first transistor collector and said second transistor base to said input, and means connecting said second transistor collector to said output.
U.S. Pat. No. 3,886,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill. The McNeill patent discloses a memory cell for a random access memory, the cell including a bistable circuit having first and second cross-coupled transistors with plural emitters. One emitter of each of the first and second transistors is coupled in common. The collector loads for the first and second transistors are provided by respective Schottky diodes which enable the differential voltage in the memory cell to remain low and the cell to be unsaturated over an order of magnitude of current increase to provide for a higher ratio of cell read current to cell store current. Additionally, hard saturation of the memory cell which would otherwise increase the write time is eliminated by this construction.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair. The Sinclair patent discloses a master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multi-layer current injection structures in integrated form.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson. The Peterson patent discloses a memory cell which comprises a word line, a pair of bit lines, a pair of current sources each having a first side coupled to a corresponding one of the bit lines; and a bistable circuit means operatively coupled to the word line and to another side of each of the current sources, whereby the bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line.
U.S. Pat. No. 4,057,789 entitled "Reference Voltage Source For Memory Cells" granted Nov. 8, 1977 to R. I. Spadavecchia and of common assignee with the subject application.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A Semiconductor Memory System" granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith. The Berger et al patent discloses a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.
IBM Technical Disclosure Bulletin publication entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1, June 1978, pages 231-2.
"Merged-Transistor Logic (MTL)-A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 340-6.
"Integrated Injection Logic: A New Approach to LSI" by Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 346-51.
"Integrated Injection Logic (I.sup.2 L)" by C. M. Hart and A. Slob, Philips Technical Review, Volume 33, 1973, No. 3, pages 76 to 85.
IBM Technical Disclosure Bulletin Publication entitled "I.sup.2 L/MTL Storage Cell Layout" by H. H. Berger et al., Vol. 22, No. 10, March 1980, pages 4604-5.
From German patent No. 2 657 561 (U.S. Pat. No. 4,122,548) a restore circuit for a semiconductor store with storage cells of bipolar transistors has become known which is characterized in that a standby reference circuit is controlled via a restore control line by a clock signal, that to the standby reference circuit an error reference circuit is connected, and that both are connected to the restore circuits via a reference line, that the levels of the voltages on the bit lines in the standby state are determined by the current flowing through two current sources which are directly connected to the bit lines and to the decoupling diodes designed as Schottky diodes, and connected to the reference line by a common cathode terminal.
This presents already a restore reference circuit for the standby state, and one for an error. One disadvantage of this circuit is that it cannot be used for integrated stores with MTL storage cells since such storages can present an additional problem, as discussed below.
For reading out the information stored in an MTL cell the latter's word line potential is decreased by several 100 mV, and at the same time a read current is applied through each one of the two existing bit lines. As the emitter-base voltages of the existing PNP transistors of all unselected storage cells are lower by approximately 0.5 V than the emitter-base voltage of the selected storage cell, practically the entire read current flows into the selected storage cell. The main effect thereof is that the emitter base voltage of one cell-PNP-transistor is higher than that of the other one. The voltage difference is indicated in the read/write amplifier. If now n unselected cells have stored a 0, there flows in spite of the practically switched-off injection current a re-injection current IR of approximately 1/2.cndot.IO.cndot.n, IO being the standby injection current of the storage cell. Owing to the high storage capacity, this re-injection current fades only slowly. So as to avoid a great influence of this parasitic read current on the reading process, the read current of the selected cell is to be high compared with the parasitic re-injection current of the unselected cell. For that reason, the standby current of the storage cell has to be kept at a very low level which e.g., in present day technique varies between 10 and 100 nA approximately. This permits a very low storage standby power, but it also comprises considerable difficulties for the restore operation, for to ensure on the one hand that the unselected cells receive enough current in a continuous selection of the storage chip for maintaining the stored information, and to make sure on the other hand that the standby current does not disturb the read process an extremely precise bit line restore operation would have to be performed. A usually performed over-control is not possible here. It has therefore been suggested in German patent application P 29 29 384.3 (U.S. Patent Application Ser. No. 167,560, filed July 11, 1980.) to provide a restore circuit via an integrated semiconductor store whose storage cells consist of bipolar transistors with PNP load elements which are arranged at the intersections of word lines and bit line pairs, that restore circuit supplying the necessary voltages for maintaining the stored information via bit and/or word reference lines as well as bit restore and/or word restore switches, which is characterized in that connected to the bit reference line and the word reference line an impedance converter is provided serving as a voltage source with a very low internal resistance, the output voltage of that impedance converter being adjusted by a group of reference storage cells preceding it.